1. Technical Field
Methods of manufacturing semiconductor devices, and more particularly methods of manufacturing semiconductor devices having an interlayer insulating film in which oxide films are stacked are disclosed.
2. Description of the Related Art
Generally, semiconductor memory devices include a memory cell array having a plurality of memory cells, and peripheral circuits for storing information on the memory cell or reading the stored information.
In the process of manufacturing the semiconductor devices, the memory cell array and the peripheral circuits are formed on a semiconductor substrate in different regions. As the degree of integration of the device is increased, however, various defects can occur due to topology differences between the memory cell region and the peripheral circuit region.
FIGS. 1A through 1C are cross-sectional views of conventional semiconductor devices for explaining a method of manufacturing a DRAM.
Referring now to FIG. 1A, a gate oxide film 2 and a gate electrode 3, which form a stacked structure, are formed on a semiconductor substrate 1. Junction regions 4 are formed in the semiconductor substrate 1 at both sides of the gate electrode 3, thus completing a transistor. The process of manufacturing the transistor is performed simultaneously at a memory cell region C and a peripheral circuit region P in the semiconductor substrate 1.
Next, a first insulating film 5 is formed on the entire structure and the first insulating film 5 is patterned so that the junction region 4 at one portion can be exposed. Thereafter, a bit line 6 is formed on the first insulating film 5 so that the bit line 6 can be connected to the exposed junction region 4. Next, a second insulating film 7 is formed on the entire structure, and the second and first insulating films 7 and 5 are then sequentially patterned so that the junction region 4 at the other portion can be exposed, thus forming a contact hole. Then, a plug 8 is formed within the contact hole.
Referring now to FIG. 1B, a third insulating film 9 is formed on the second insulating film 7 including the plug 8. Then, the third insulating film 9 is patterned to expose the plug 8. Next, a lower electrode 10 of a capacitor is formed on the third insulating film 9 so that the lower electrode 10 can be connected to the plug 8. At this time, the third insulating film 9 is made of a PE-TEOS oxide film.
By reference to FIG. 1C, a dielectric film 11 and an upper electrode 12 are sequentially formed on the third insulating film 9 including the lower electrode 10 and are then patterned to complete the capacitor. At this time, as the wet etch rate of the PE-TEOS oxide film 9 is slow, the third insulating film 9 in the peripheral circuit region P remains. Therefore, the topology difference between the cell region C and the peripheral circuit region P needs to be decreased.
Thereafter, a fourth insulating film 13 is formed on the entire structure. Then, the fourth, third, second and first insulating films 13, 9, 7 and 5 are sequentially patterned to form a contact hole 14 so that a given portion of the gate electrode 3 in the peripheral circuit region P can be exposed. Next, a metal wire (not shown) is formed on the fourth insulating film 13 so that the metal wire can be connected to the gate electrode 3 via a contact hole 14. At this time, the fourth insulating film 13 is also made of a PE-TEOS oxide film.
However, in the above conventional process, the topology angle at the boundary of the memory cell region C and the peripheral circuit region P becomes about 45° due to the height of the upper electrode 12 in the capacitor. Therefore, as the topology difference is reflected on the surface of the fourth insulating film 13 made of the PE-TEOS oxide film, a conductive material may remain or defects can occur in the lithography process and etch process for forming the metal wire when the plug for connecting with a subsequent metal wire is formed. Thus, a bridge, etc. is generated and contact between the metal wires or defects in the wire may be caused.
Further, as the upper electrode 12 is formed with the third insulating film 9 in the peripheral circuit region P exposed, the surface state of the third insulating film 9 becomes rough through various processes (lithograph process, etch process, etc.), thus degrading an interface characteristic with the fourth insulating film 13. Therefore, in a cleaning process that is performed after the contact hole 14 is formed, an etch agent penetrates into the interface of the third and fourth insulating films 9 and 13, so that an etch portion A of an undesired ring shape is formed. As a result, connection to a neighboring contact hole is made difficult because of the bridge or poor step coverage of a barrier metal layer (Ti/TiN) in the contact hole 14 as a result of the deformity shown at A.
Meanwhile, after the fourth insulating film 13 is formed, a rapid thermal annealing (RTA) or a tube annealing for activating the upper electrode 12 is performed at the temperature of 800° C. However, this has no significant effect on reduction in the topology difference of the PE-TEOS oxide film surface or an increase in the adhesive force between the PE-TEOS oxide films.